1. Field of the Invention
The present invention relates to a floating gate type nonvolatile semiconductor memory achieving an improvement in a data write circuit.
2. Description of the Related Art
A floating gate type nonvolatile semiconductor memory assumes a structure achieved by two-dimensionally arraying memory cells each having a control gate electrode and a floating gate electrode embedded in an insulating film laminated one on top of the other. A floating gate type nonvolatile semiconductor memory is used in application as various types of read only memory (ROM) that allow an overwrite.
A floating gate type nonvolatile semiconductor memory in the related art adopts the following structure. A memory cell array is constituted of a plurality of memory cells (MC0, MC1, . . . ) provided in a matrix pattern, a plurality of bit lines (BL0, BL1, . . . ) and a plurality of word lines (WL0, WL1, . . . ) each connected to the individual memory cells. The plurality of word lines are each connected to rows of gate electrodes of the memory cells.
A cell drain voltage source supplies a voltage to be applied to the drain electrode of each of the memory cells (MC0, MC1, . . . ). A xe2x80x9cPGMYBxe2x80x9d signal and a xe2x80x9cRSTxe2x80x9d signal which are to be detailed later are input to the cell drain voltage source. In this specification and the attached drawings, the voltage supply terminal at the cell drain voltage source and the voltage supplied through the voltage supply terminal are both referred to as xe2x80x9cCDVxe2x80x9d, unless otherwise specified.
One CDV supplied from the cell drain voltage source is exclusively connected to the drain electrodes of even-numbered memory cells or odd-numbered memory cells among the memory cells (MC0, MC1, . . . ) through a plurality of select lines (SL0, SL1 . . . ) in units of individual rows. Another CDV supplied from the cell drain voltage source is connected to the plurality of bit lines (BL0, BL1, . . . ) sequentially via a data write circuit and a multiplexer circuit. The bit lines (BL0, BL1, . . . ) are each connected to one row of source electrodes of the memory cells (MC0, MC1, . . . ).
The data write circuit is employed to write xe2x80x9c0xe2x80x9d data or xe2x80x9c1xe2x80x9d data into each memory cell. In addition to the CDV, the xe2x80x9cPGMYBxe2x80x9d and xe2x80x9cRSTxe2x80x9d signals to be detailed later and the xe2x80x9c0xe2x80x9d data or the xe2x80x9c1xe2x80x9d data are input to the data write circuit.
The multiplexer circuit selects a given bit line through which the voltage from the cell drain voltage source is to be supplied and connects the cell drain voltage source to the selected bit line.
Hereafter, xe2x80x9cLxe2x80x9d indicates the xe2x80x9cground levelxe2x80x9d and xe2x80x9cHxe2x80x9d indicates the xe2x80x9csource voltage levelxe2x80x9d in the specification and the attached drawings unless otherwise specified.
The xe2x80x9cPGMYBxe2x80x9d signal input to the cell drain voltage source and the data write circuit shifts to xe2x80x9cLxe2x80x9d during a write operation. In addition, the xe2x80x9cRSTxe2x80x9d signal input to the cell drain voltage source and the data write circuit is set to xe2x80x9cHxe2x80x9d level over a specific period when the xe2x80x9cPGMYBxe2x80x9d signal shifts from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d. The specific length of time over which the xe2x80x9cRSTxe2x80x9d is sustained at xe2x80x9cHxe2x80x9d level is set to a length of time that is long enough for the voltage at the bit line charged through the write operation to come down to the ground level. A xe2x80x9cBLPZAxe2x80x9d indicates a node that connects the data write circuit with the multiplexer circuit.
During the write operation, the cell drain voltage source supplies a write voltage, e.g., 4.5V, if xe2x80x9cLxe2x80x9d is input to a xe2x80x9cPGMYBxe2x80x9d which is controlled by the xe2x80x9cPGMYBxe2x80x9d signal. If, on the other hand, xe2x80x9cHxe2x80x9d is input to the xe2x80x9cPGMYBxe2x80x9d, a read voltage, e.g., 1.0V, is supplied. In addition, the voltage supply from the cell drain voltage source is suspended while the xe2x80x9cRSTxe2x80x9d signal is at xe2x80x9cHxe2x80x9d, thereby setting the CDV to the ground level. A low through rate is set for the write voltage (CDV) in order to prevent a write error.
When writing the xe2x80x9c0xe2x80x9d data, electrons are injected into the floating gate by applying the 4.5V voltage between the drain electrode and the source electrode at the memory cell. However, if the voltage applied between the drain electrode and the source electrode of the memory cell is equal to or lower than 1.5V, no electrons are injected into the floating gate and the xe2x80x9c1xe2x80x9d data are written. While xe2x80x9c0xe2x80x9d indicates the state in which a electrons are injected in the following description, it goes without saying that the xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d settings may be reversed.
Now, a data write operation performed at the MC0 is explained. The write operation is performed by inputting xe2x80x9cLxe2x80x9d to the xe2x80x9cPGMYBxe2x80x9d and applying the 4.5V voltage to the drain electrode of the MC0. The multiplexer circuit connects the BL0 xe2x80x9cBLPZAxe2x80x9d.
When writing the xe2x80x9c1xe2x80x9d data, the data write circuit raises the voltage at the xe2x80x9cBLPZAxe2x80x9d in conformance to the CDV until the voltage is ultimately biased to 3V. As a result, 1.5V is applied between the drain electrode and the source electrode at the MC0 and no electrons are injected into the floating gate.
When writing the xe2x80x9c0xe2x80x9d data on the other hand, the data write circuit sets the xe2x80x9cBLPZAxe2x80x9d to the ground level xe2x80x9cLxe2x80x9d. Consequently, a 4.5V voltage is applied between the drain electrode and the source electrode at the MC0, thereby allowing electrons to be injected into the floating gate of the MC0.
During the write operation, the xe2x80x9cdata write cyclexe2x80x9d and the xe2x80x9cverify cyclexe2x80x9d in which the data that have been written are verified are alternately repeated. When the operation shifts from the data write cycle to the verify cycle, the xe2x80x9cPGMYBxe2x80x9d signal shifts from xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d, thereby setting the xe2x80x9cRSTxe2x80x9d signal to xe2x80x9cHxe2x80x9d over the specific length of time. When the xe2x80x9cRSTxe2x80x9d signal is set to xe2x80x9cHxe2x80x9d, the data write circuit connects the xe2x80x9cBLPZAxe2x80x9d to the CDV. Thus, as the CDV shifts to the ground level xe2x80x9cLxe2x80x9d, the xe2x80x9cBLPZAxe2x80x9d, too, shifts to the ground level xe2x80x9cLxe2x80x9d. The data write operation is performed as described above.
As further miniaturization is pursued in semiconductor processes in recent years, the unit length resistance at a bit line has been increasing. This tendency is particularly prominent in a memory with a larger capacity. Since the bit line current generated during a data write operation is significant, the extent to which the voltage becomes lowered through the bit line becomes further pronounced. For this reason, even when the BLPZA is grounded, the voltage is allowed to float by the degree corresponding to the bit line resistance from the ground level at a bit line end distanced from the BLPZA. When this happens, the required level of a voltage is not applied to the drain and the source of the memory cell and, in addition, the difference in the potential between the gate electrode and the source electrode becomes reduced. Thus, a problem arises in that an incomplete write occurs, thereby inducing a write error.
Accordingly, an object of the present invention is to provide a floating gate type nonvolatile semiconductor memory that allows a reliable data write and reduces the occurrence of a write error even in a large-capacity memory manufactured through a semiconductor process pursuing further miniaturization by making an improvement on the bit line settings in the related art.
In order to achieve the object described above, in the floating gate type nonvolatile semiconductor memory according to the present invention having a memory cell array constituted of a plurality of memory cells arrayed in a matrix pattern, a plurality of bit lines and a plurality of word lines each connected to the individual memory cells, the plurality of word lines are connected to a row of gate electrodes of memory cells with one voltage supplied from a cell drain voltage source exclusively connected to drain electrodes of even-numbered memory cells or odd-numbered memory cells through a plurality of select lines in units of individual rows, another voltage supplied from the cell drain voltage source is connected to the plurality of bit lines sequentially via a data write circuit and a multiplexer circuit, the bit lines are each connected to a row source electrodes of the memory cells in units of individual rows and at least two sets each constituted of a data write circuit and a multiplexer circuit are provided with at least one set connected to the two ends of the plurality of bit lines on each side.